As technology nodes decrease, the density of features on a substrate increases. The decreased spacing between features on the substrate can result in the separation of a layout design into multiple patterns due to resolution constraints. A conventional lithographic arrangement, including a single reticle edge masking assembly, is only capable of transferring one pattern at a time.
The reticle edge masking assembly includes a slit extending across substantially the entire width of the reticle masking element. The slit can translate along a length direction, perpendicular to the width of the reticle masking element. The translation of the slit sequentially illuminates portions of a mask whose pattern is transferred to a wafer. During a patterning process, the wafer moves in a direction opposite to the direction of translation of the slit.
Often a pattern is repeated many times on a single wafer. Each time a pattern is repeated the slit is reset to an original position, or the direction of wafer movement is reversed. To maximize throughput the movement direction of the wafer is often reversed. However, this arrangement causes particles to build up on a surface of the wafer. The build up of particles can block illumination passing through the reticle masking element, resulting in an error in the pattern transfer.
In order to transfer multiple patterns to the wafer, the mask in the lithographic arrangement is replaced for each pattern, or multiple lithographic arrangements are used with each having a separate pattern. The replacement of masks or the use of multiple lithographic arrangements increases production time and cost.